This invention relates to a circuit for generating a delay in a periodic pulse such that the pulse width is expanded by a chosen factor of multiplication.
The components of semiconductor devices are controlled by various signals. The pulse width of these signals is often quite important for the proper operation of the components and the semiconductor device.
For instance, in asynchronous SRAM devices the Edge Transition Detection (ETD) signal is often used as the internal clock of the device, allowing the device to operate internally in a synchronous manner. If the pulse width of the ETD signal is too wide or too narrow, the memory device will not be able to function properly.
Address transition detection (ATD) circuits are used to detect a change in user-supply address bits in memory devices. The pulse from the ATD circuit is often used to precharge the data path to and from the memory address for the transfer of data. If the ATD signal pulse width is too narrow, the pulse is insufficient to precharge the data path.
It would be desirable to be able to modulate the pulse width of a signal so the signal could be used to accurately serve as a device""s internal clock or detect an address transition and precharge a memory. Expanding a narrow pulse width would also be useful for measuring signals with narrow pulse widths.
The prior art has addressed controlling pulse widths. For instance, U.S. Pat. No. 5,995,444 to McClure discusses controlling the width of an ETD pulse of a memory device by varying the logic state of one or more control signals of the memory device. By changing the combination of logic states of the control signals, the pulse width of the ETD signal may be varied to produce an optimal ETD pulse width.
U.S. Pat. No. 5,706,246 to Choi et al. discusses producing an ATD signal of sufficient width to stably operate an internal circuit. An input signal is delayed until its pulse width is of sufficient duration to prevent malfunction of a memory device.
The prior art discussed here discusses expanding pulse widths by determining the desired pulse width and then varying the input signal to produce the desired pulse width. The output pulse width is not dependent on the input pulse width. The prior art discussed here does not provide a mechanism for multiplying the width of the input signal by a known factor.
It is an object of this invention to provide a method and system for expanding an input signal""s pulse width by a known factor.
The object is achieved by a circuit which generates a delay equal to the pulse width of the input signal for both a SHIFT and OUT signal, which are out of phase with each other. The delay is generated when a capacitor applies voltage to two control transistors in both the SHIFT and OUT blocks, reducing gate control in these transistors and generating a delay in the falling edge of these signals such that the pulse width of the SHIFT signal is reduced and the pulse width of the OUT signal is increased. The capacitor is charged by a transistor activated by the SHIFT signal. The pulse-doubling system is self-converging: when the SHIFT signal""s pulse width is zero, the OUT signal""s pulse width is doubled, and the capacitor""s charging level is fixed since it is no longer charged by the transistor controlled by the SHIFT signal. The circuit may be modified to provide greater pulse width expansion. This circuit may be employed in CMOS submicron technologies.